1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a p-channel NAND flash memory and operating method thereof.
2. Description of the Related Art
Flash memory devices are applicable for multiple operations of data writing, reading and erasing, and have the advantage that stored data will not been vanished even after power supply is cut off. Thus, flash memory devices are widely used as non-volatile memory devices for personal computers and other electronic facilities.
In a conventional flash memory device, doped poly-silicon is used for fabricating floating gate and control gate. The control gate is formed directly on the floating gate, a dielectric layer is used to insulate the control gate from the floating gate, and a tunneling oxide layer is used to separate the floating gate from the substrate of the device; such device is commonly called stacked gate flash memory.
Flash memory devices can be categorized structurally as p-channel memory devices and n-channel memory devices. Wherein, the p-channel memory devices have certain features distinguishable from that of n-channel memory devices, such as high electron injection efficiency, high scalability, and low tunneling oxide electric filed. Furthermore, the p-channel memory devices can be used to avoid problems in device reliability induced by hot electron hole injection.
During a programming operation for a p-channel memory device, a method of channel hot electron injection (CHEI) or source-side injection (SSI) is usually used for injecting electrons into the floating gate. During an erasing operation, F-N tunneling is utilized to force all of the electrons distributed in the floating gate to pass the tunneling oxide into the substrate. For the CHEI, however, electron injection efficiency is low, and a relatively high operating voltage is required. For the SSI, on the other hand, the size of the devices will be continuingly miniaturized and the coupling capacity between gates of the devices will be reduced with enhancement of the integration of the devices; thus, during a programming operation, the vertical electric field between the control gate and the substrate will be insufficient and thus to slow down the progress of the programming operation.
On the other hand, flash memory arrays that are often used in the manufacturing industries include NOR (Not-OR) and NAND (Not-AND) arrays. The NAND array is higher in its integration comparing to NOR array, because cells in an NAND memory are in series connection. For an NAND array, however, the procedures of memory cells programming and data writing/erasing are more complicated. Conventionally, operations of memory cells programming and data erasing in an NAND array are carried out via F-N (Fowler-Nordheim) tunneling to cause electrons to pass through the tunneling oxide and enter into the floating gate, and further into the substrate, such that, during a high voltage operation, the tunneling oxide will sustain damages and reliability of which will be reduced. Moreover, since many memory cells are in series connection in the array, electric current of reading operation for memory cells becomes weaker, which will slow down the operation of the memory cells, and adversely affect the efficiency of the entire device.